Gate oxide thickness dependence of hot carrier induced degradation on PMOSFETs

Y. Hiruta*, H. Oyamatsu, H. S. Momose, H. Iwai, K. Maeguchi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Gate oxide thickness dependences of pMOSFET hot carrier degradation characteristics were studied at 300K and 77K. It was found that a thin gate oxide pMOSFET shows superior characteristics regarding hot carrier degradation. Threshold voltage shift becomes very small, with reduction in the gate oxide thickness, due to the tunneling effect. Interface state generation increases with the gate oxide thickness reduction. Fortunately, however, it is not enough to affect device characteristics. It was found that the interface state increase is described by the gate current uniquely, independently from the gate oxide thickness, bias condition, and temperature.

Original languageEnglish
Title of host publicationESSDERC 1989 - Proceedings of the 19th European Solid State Device Research Conference
EditorsAnton Heuberger, Heiner Ryssel, Peter Lange
PublisherIEEE Computer Society
Pages732-735
Number of pages4
ISBN (Electronic)0387510001
ISBN (Print)9780387510002
DOIs
StatePublished - 1989
Event19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany
Duration: 11 Sep 198914 Sep 1989

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference19th European Solid State Device Research Conference, ESSDERC 1989
Country/TerritoryGermany
CityBerlin
Period11/09/8914/09/89

Fingerprint

Dive into the research topics of 'Gate oxide thickness dependence of hot carrier induced degradation on PMOSFETs'. Together they form a unique fingerprint.

Cite this