Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Chia Tsung Tso; Tung Yu Liu; Jeng-Tzong Sheu

doi:10.7567/JJAP.54.06FG06

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Chia Tsung Tso
, Tung Yu Liu
, Jeng-Tzong Sheu^*

^*Corresponding author for this work

Institute of Biomedical Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25μm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13mV/V), and a high I_ON/I_OFF current ratio (∼1 × 10⁹) under a relatively low voltage condition (V_D = 0.3V, V_G = 5V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

Original language	English
Article number	06FG06
Journal	Japanese journal of applied physics
Volume	54
Issue number	6
DOIs	https://doi.org/10.7567/JJAP.54.06FG06
State	Published - 1 Jun 2015

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title = "Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels",

abstract = "Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25μm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3V, VG = 5V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.",

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T1 - Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

AU - Tso, Chia Tsung

AU - Liu, Tung Yu

AU - Sheu, Jeng-Tzong

PY - 2015/6/1

Y1 - 2015/6/1

N2 - Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25μm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3V, VG = 5V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

AB - Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25μm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3V, VG = 5V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

UR - https://www.scopus.com/pages/publications/84930698418

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DO - 10.7567/JJAP.54.06FG06

M3 - Article

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SN - 0021-4922

VL - 54

JO - Japanese journal of applied physics

JF - Japanese journal of applied physics

IS - 6

M1 - 06FG06

ER -

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

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