Gate-All-Around In0.53Ga0.47As Junctionless Nanowire FET with Tapered Source/Drain Structure

Kian Hui Goh; Sachin Yadav; Kain Lu Low; Gengchiau Liang; Xiao Gong; Yee Chia Yeo

doi:10.1109/TED.2016.2526778

Gate-All-Around In_0.53Ga_0.47As Junctionless Nanowire FET with Tapered Source/Drain Structure

Kian Hui Goh, Sachin Yadav, Kain Lu Low, Gengchiau Liang, Xiao Gong^*, Yee Chia Yeo

^*Corresponding author for this work

Institute of Pioneer Semiconductor Innovation

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (L_CH), NW height (H_NW), and NW width (W_NW) were realized. Despite having a large equivalent oxide thickness of ∼ 4.5 nm, high extrinsic transconductance (_m,ext) of 820 μSμm was achieved at V_D of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (R_SD) of 275 Ωμ m, which is one of the lowest among the reported 3-D InGaAs MOSFETs.

Original language	English
Article number	7407624
Pages (from-to)	1027-1033
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	3
DOIs	https://doi.org/10.1109/TED.2016.2526778
State	Published - Mar 2016

Keywords

In0.53Ga0.47As n-channel FET (nFET)
junctionless nanowire FET (JL-NWFET) with tapered source/drain (S/D) structure
sub-15-nm channel length.

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10.1109/TED.2016.2526778

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@article{c1866ec3ad4d4260ad66f16fa6f182aa,

title = "Gate-All-Around In0.53Ga0.47As Junctionless Nanowire FET with Tapered Source/Drain Structure",

abstract = "A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (LCH), NW height (HNW), and NW width (WNW) were realized. Despite having a large equivalent oxide thickness of ∼ 4.5 nm, high extrinsic transconductance (m,ext) of 820 μSμm was achieved at VD of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (RSD) of 275 Ωμ m, which is one of the lowest among the reported 3-D InGaAs MOSFETs.",

keywords = "In0.53Ga0.47As n-channel FET (nFET), junctionless nanowire FET (JL-NWFET) with tapered source/drain (S/D) structure, sub-15-nm channel length.",

author = "Goh, {Kian Hui} and Sachin Yadav and Low, {Kain Lu} and Gengchiau Liang and Xiao Gong and Yeo, {Yee Chia}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.",

year = "2016",

month = mar,

doi = "10.1109/TED.2016.2526778",

language = "English",

volume = "63",

pages = "1027--1033",

journal = "IEEE Transactions on Electron Devices",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - Gate-All-Around In0.53Ga0.47As Junctionless Nanowire FET with Tapered Source/Drain Structure

AU - Goh, Kian Hui

AU - Yadav, Sachin

AU - Low, Kain Lu

AU - Liang, Gengchiau

AU - Gong, Xiao

AU - Yeo, Yee Chia

PY - 2016/3

Y1 - 2016/3

N2 - A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (LCH), NW height (HNW), and NW width (WNW) were realized. Despite having a large equivalent oxide thickness of ∼ 4.5 nm, high extrinsic transconductance (m,ext) of 820 μSμm was achieved at VD of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (RSD) of 275 Ωμ m, which is one of the lowest among the reported 3-D InGaAs MOSFETs.

AB - A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (LCH), NW height (HNW), and NW width (WNW) were realized. Despite having a large equivalent oxide thickness of ∼ 4.5 nm, high extrinsic transconductance (m,ext) of 820 μSμm was achieved at VD of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (RSD) of 275 Ωμ m, which is one of the lowest among the reported 3-D InGaAs MOSFETs.

KW - In0.53Ga0.47As n-channel FET (nFET)

KW - junctionless nanowire FET (JL-NWFET) with tapered source/drain (S/D) structure

KW - sub-15-nm channel length.

UR - http://www.scopus.com/inward/record.url?scp=84976207499&partnerID=8YFLogxK

U2 - 10.1109/TED.2016.2526778

DO - 10.1109/TED.2016.2526778

M3 - Article

AN - SCOPUS:84976207499

SN - 0018-9383

VL - 63

SP - 1027

EP - 1033

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

M1 - 7407624

ER -

Gate-All-Around In_0.53Ga_0.47As Junctionless Nanowire FET with Tapered Source/Drain Structure

Abstract

Keywords

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