TY - GEN
T1 - Full chip power benefits with negative capacitance FETs
AU - Samal, Sandeep K.
AU - Khandelwal, Sourabh
AU - Khan, Asif I.
AU - Salahuddin, Sayeef
AU - Hu, Chen-Ming
AU - Lim, Sung Kyu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/8/11
Y1 - 2017/8/11
N2 - We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.
AB - We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.
UR - http://www.scopus.com/inward/record.url?scp=85028587338&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2017.8009170
DO - 10.1109/ISLPED.2017.8009170
M3 - Conference contribution
AN - SCOPUS:85028587338
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Y2 - 24 July 2017 through 26 July 2017
ER -