Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Chun Chieh Huang; Shao Hang Hung; Jen Feng Chung; Lan-Da Van; Chin Teng Lin

doi:10.1109/ISCAS.2008.4542018

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Chun Chieh Huang^*, Shao Hang Hung, Jen Feng Chung, Lan-Da Van, Chin Teng Lin

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

27 Scopus citations

Abstract

We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 μm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 μW under ±1.5V supply.

Original language	English
Title of host publication	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages	2717-2720
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2008.4542018
State	Published - 2008
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States Duration: 18 May 2008 → 21 May 2008

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/Territory	United States
City	Seattle, WA
Period	18/05/08 → 21/05/08

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10.1109/ISCAS.2008.4542018

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Huang, C. C., Hung, S. H., Chung, J. F., Van, L.-D., & Lin, C. T. (2008). Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (pp. 2717-2720). Article 4542018 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4542018

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title = "Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition",

abstract = "We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 μm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 μW under ±1.5V supply.",

author = "Huang, {Chun Chieh} and Hung, {Shao Hang} and Chung, {Jen Feng} and Lan-Da Van and Lin, {Chin Teng}",

year = "2008",

doi = "10.1109/ISCAS.2008.4542018",

language = "English",

isbn = "9781424416844",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2717--2720",

booktitle = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008",

note = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 ; Conference date: 18-05-2008 Through 21-05-2008",

}

Huang, CC, Hung, SH, Chung, JF, Van, L-D & Lin, CT 2008, Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition. in 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008., 4542018, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2717-2720, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 18/05/08. https://doi.org/10.1109/ISCAS.2008.4542018

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition. / Huang, Chun Chieh; Hung, Shao Hang; Chung, Jen Feng et al.
2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. 2008. p. 2717-2720 4542018 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Van, Lan-Da

AU - Lin, Chin Teng

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N2 - We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 μm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 μW under ±1.5V supply.

AB - We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 μm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 μW under ±1.5V supply.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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ER -

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

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