TY - GEN
T1 - FPGA implementation of OFDM baseband processor
AU - Sung, Kuohua
AU - Hsu, Terng-Yin
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/18
Y1 - 2017/10/18
N2 - This paper explains how to use a field programmable gate array (FPGA) evaluation board, which has limited resources, to build a reduced version of the OFDM baseband processor platform. The contribution in this paper is to propose conversion approaches and establish that these efficient approaches can be used to translate the design of the silicon OFDM-baseband processor into the design of a FPGA. The innovation in this paper is in providing a simple and effective way to accomplish a pipelined divider on an FPGA.
AB - This paper explains how to use a field programmable gate array (FPGA) evaluation board, which has limited resources, to build a reduced version of the OFDM baseband processor platform. The contribution in this paper is to propose conversion approaches and establish that these efficient approaches can be used to translate the design of the silicon OFDM-baseband processor into the design of a FPGA. The innovation in this paper is in providing a simple and effective way to accomplish a pipelined divider on an FPGA.
KW - CE: Clock Enable
KW - IP: Intellectual Property OFDM: Orthogonal Frequency-Division Multiplexing
KW - LUT: Look-Up Table
KW - MIMO: Multpile-Input and Multiple-Output
KW - MMCM: Mixed-Mode Clock Manager
KW - OR1200: OpenRISC 1200
KW - RALU: Reconfigurable Arithmatic Logic Unit
UR - http://www.scopus.com/inward/record.url?scp=85039912578&partnerID=8YFLogxK
U2 - 10.1109/DESEC.2017.8073864
DO - 10.1109/DESEC.2017.8073864
M3 - Conference contribution
AN - SCOPUS:85039912578
T3 - 2017 IEEE Conference on Dependable and Secure Computing
SP - 466
EP - 467
BT - 2017 IEEE Conference on Dependable and Secure Computing
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Conference on Dependable and Secure Computing
Y2 - 7 August 2017 through 10 August 2017
ER -