Flash memory scaling: From material selection to performance improvement

Tuo-Hung Hou; Jaegoo Lee; Jonathan T. Shaw; Edwin C. Kan

doi:10.1557/PROC-1071-F02-01

Flash memory scaling: From material selection to performance improvement

Tuo-Hung Hou^*, Jaegoo Lee, Jonathan T. Shaw, Edwin C. Kan

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm ²) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

Original language	English
Title of host publication	Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories
Pages	3-15
Number of pages	13
DOIs	https://doi.org/10.1557/PROC-1071-F02-01
State	Published - Mar 2008
Event	Materials Science and Technology for Nonvolatile Memories - San Francisco, CA, United States Duration: 24 Mar 2008 → 27 Mar 2008

Publication series

Name	Materials Research Society Symposium Proceedings
Volume	1071
ISSN (Print)	0272-9172

Conference

Conference	Materials Science and Technology for Nonvolatile Memories
Country/Territory	United States
City	San Francisco, CA
Period	24/03/08 → 27/03/08

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10.1557/PROC-1071-F02-01

Cite this

@inproceedings{7c09f2a017c34d2fb26f1610eba4acd7,

title = "Flash memory scaling: From material selection to performance improvement",

abstract = "Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.",

author = "Tuo-Hung Hou and Jaegoo Lee and Shaw, {Jonathan T.} and Kan, {Edwin C.}",

year = "2008",

month = mar,

doi = "10.1557/PROC-1071-F02-01",

language = "English",

isbn = "9781605110417",

series = "Materials Research Society Symposium Proceedings",

pages = "3--15",

booktitle = "Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories",

note = "Materials Science and Technology for Nonvolatile Memories ; Conference date: 24-03-2008 Through 27-03-2008",

}

Hou, T-H, Lee, J, Shaw, JT & Kan, EC 2008, Flash memory scaling: From material selection to performance improvement. in Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories. Materials Research Society Symposium Proceedings, vol. 1071, pp. 3-15, Materials Science and Technology for Nonvolatile Memories, San Francisco, CA, United States, 24/03/08. https://doi.org/10.1557/PROC-1071-F02-01

Flash memory scaling: From material selection to performance improvement. / Hou, Tuo-Hung; Lee, Jaegoo; Shaw, Jonathan T. et al.
Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories. 2008. p. 3-15 (Materials Research Society Symposium Proceedings; Vol. 1071).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Flash memory scaling

T2 - Materials Science and Technology for Nonvolatile Memories

AU - Hou, Tuo-Hung

AU - Lee, Jaegoo

AU - Shaw, Jonathan T.

AU - Kan, Edwin C.

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Y1 - 2008/3

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AB - Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

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DO - 10.1557/PROC-1071-F02-01

M3 - Conference contribution

AN - SCOPUS:55849125777

SN - 9781605110417

T3 - Materials Research Society Symposium Proceedings

SP - 3

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BT - Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories

Y2 - 24 March 2008 through 27 March 2008

ER -

Flash memory scaling: From material selection to performance improvement

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