Flash memory scaling: From material selection to performance improvement

Tuo-Hung Hou*, Jaegoo Lee, Jonathan T. Shaw, Edwin C. Kan

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Abstract

    Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

    Original languageEnglish
    Title of host publicationMaterials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories
    Pages3-15
    Number of pages13
    DOIs
    StatePublished - Mar 2008
    EventMaterials Science and Technology for Nonvolatile Memories - San Francisco, CA, United States
    Duration: 24 Mar 200827 Mar 2008

    Publication series

    NameMaterials Research Society Symposium Proceedings
    Volume1071
    ISSN (Print)0272-9172

    Conference

    ConferenceMaterials Science and Technology for Nonvolatile Memories
    Country/TerritoryUnited States
    CitySan Francisco, CA
    Period24/03/0827/03/08

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