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Fixed-width multiplier for DSP application
Shyh-Jye Jou
*
, Hui Hsuan Wang
*
Corresponding author for this work
Institute of Electronics
Research output
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Contribution to conference
›
Paper
›
peer-review
38
Scopus citations
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Keyphrases
Compensation Method
100%
Digital Signal Processing
100%
Signal Processing Applications
100%
Fixed-width multiplier
100%
Proposed Architecture
50%
Operation Speed
50%
Low Computational Complexity
50%
New Architecture
50%
Hardware Complexity
50%
Low Error
50%
Booth multiplier
50%
Array multiplier
50%
Fast Operation
50%
Engineering
Digital Signal Processing
100%
Signal Processing Application
100%
Speed Operation
50%
Hardware Complexity
50%
Hardware Overhead
50%
Design Result
50%
Computer Science
Digital Signal Processing
100%
Signal Processing Application
100%
Hardware Overhead
50%
Computer Hardware
50%