Fixed-width multiplier for DSP application

Shyh-Jye Jou; Hui Hsuan Wang

doi:10.1109/ICCD.2000.878302

Fixed-width multiplier for DSP application

Shyh-Jye Jou^*, Hui Hsuan Wang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

38 Scopus citations

Abstract

A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

Original language	English
Pages	318-322
Number of pages	5
DOIs	https://doi.org/10.1109/ICCD.2000.878302
State	Published - 1 Jan 2000
Event	2000 International Conference on Computer Design - Austin, TX, USA Duration: 17 Sep 2000 → 20 Sep 2000

Conference

Conference	2000 International Conference on Computer Design
City	Austin, TX, USA
Period	17/09/00 → 20/09/00

Access to Document

10.1109/ICCD.2000.878302

Cite this

@conference{04bcffdb937f4f6fae71406d43ded41f,

title = "Fixed-width multiplier for DSP application",

abstract = "A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.",

author = "Shyh-Jye Jou and Wang, {Hui Hsuan}",

year = "2000",

month = jan,

day = "1",

doi = "10.1109/ICCD.2000.878302",

language = "English",

pages = "318--322",

note = "2000 International Conference on Computer Design ; Conference date: 17-09-2000 Through 20-09-2000",

}

TY - CONF

T1 - Fixed-width multiplier for DSP application

AU - Jou, Shyh-Jye

AU - Wang, Hui Hsuan

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

AB - A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

UR - http://www.scopus.com/inward/record.url?scp=0033681072&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2000.878302

DO - 10.1109/ICCD.2000.878302

M3 - Paper

AN - SCOPUS:0033681072

SP - 318

EP - 322

T2 - 2000 International Conference on Computer Design

Y2 - 17 September 2000 through 20 September 2000

ER -

Fixed-width multiplier for DSP application

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this