First experimental Ge CMOS FinFETs directly on SOI substrate

Cheng Ting Chung; Che Wei Chen; Jyun Chih Lin; Che Chen Wu; Chao-Hsin Chien; Guang Li Luo

doi:10.1109/IEDM.2012.6479054

First experimental Ge CMOS FinFETs directly on SOI substrate

Cheng Ting Chung^*, Che Wei Chen, Jyun Chih Lin, Che Chen Wu, Chao-Hsin Chien, Guang Li Luo

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L_channel =120nm and Fin width=40nm with high I_on/I_off ratio (>10⁵), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n-and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L _channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.

Original language	English
Title of host publication	2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages	16.4.1-16.4.4
DOIs	https://doi.org/10.1109/IEDM.2012.6479054
State	Published - 2012
Event	2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States Duration: 10 Dec 2012 → 13 Dec 2012

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2012 IEEE International Electron Devices Meeting, IEDM 2012
Country/Territory	United States
City	San Francisco, CA
Period	10/12/12 → 13/12/12

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10.1109/IEDM.2012.6479054

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@inproceedings{a32dc8c7365748989bd832f6b716f542,

title = "First experimental Ge CMOS FinFETs directly on SOI substrate",

abstract = "High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of Lchannel =120nm and Fin width=40nm with high Ion/Ioff ratio (>105), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n-and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.",

author = "Chung, {Cheng Ting} and Chen, {Che Wei} and Lin, {Jyun Chih} and Wu, {Che Chen} and Chao-Hsin Chien and Luo, {Guang Li}",

year = "2012",

doi = "10.1109/IEDM.2012.6479054",

language = "English",

isbn = "9781467348706",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "16.4.1--16.4.4",

booktitle = "2012 IEEE International Electron Devices Meeting, IEDM 2012",

note = "2012 IEEE International Electron Devices Meeting, IEDM 2012 ; Conference date: 10-12-2012 Through 13-12-2012",

}

Chung, CT, Chen, CW, Lin, JC, Wu, CC, Chien, C-H & Luo, GL 2012, First experimental Ge CMOS FinFETs directly on SOI substrate. in 2012 IEEE International Electron Devices Meeting, IEDM 2012., 6479054, Technical Digest - International Electron Devices Meeting, IEDM, pp. 16.4.1-16.4.4, 2012 IEEE International Electron Devices Meeting, IEDM 2012, San Francisco, CA, United States, 10/12/12. https://doi.org/10.1109/IEDM.2012.6479054

First experimental Ge CMOS FinFETs directly on SOI substrate. / Chung, Cheng Ting; Chen, Che Wei; Lin, Jyun Chih et al.
2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 16.4.1-16.4.4 6479054 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - First experimental Ge CMOS FinFETs directly on SOI substrate

AU - Chung, Cheng Ting

AU - Chen, Che Wei

AU - Lin, Jyun Chih

AU - Wu, Che Chen

AU - Chien, Chao-Hsin

AU - Luo, Guang Li

PY - 2012

Y1 - 2012

N2 - High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of Lchannel =120nm and Fin width=40nm with high Ion/Ioff ratio (>105), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n-and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.

AB - High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of Lchannel =120nm and Fin width=40nm with high Ion/Ioff ratio (>105), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n-and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.

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U2 - 10.1109/IEDM.2012.6479054

DO - 10.1109/IEDM.2012.6479054

M3 - Conference contribution

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SN - 9781467348706

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 16.4.1-16.4.4

BT - 2012 IEEE International Electron Devices Meeting, IEDM 2012

T2 - 2012 IEEE International Electron Devices Meeting, IEDM 2012

Y2 - 10 December 2012 through 13 December 2012

ER -

First experimental Ge CMOS FinFETs directly on SOI substrate

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