First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

X. R. Yu, W. H. Chang, T. C. Hong, P. J. Sung, A. Agarwal, G. L. Luo, C. T. Wu, K. H. Kao, C. J. Su, S. W. Chang, W. H. Lu, P. Y. Fu, J. H. Lin, P. H. Wu, T. C. Cho, W. C.Yu Ma, D. D. Lu, T. S. Chao, T. Maeda, Y. J. LeeW. F. Wu, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

To solve the mobility balance issue in nanosheet FETs (NSFETs) and complementary FETs (CFETs), the aggressive approach using hetero-oriented integration with Ge channels was demonstrated by low temperature hetero-layer bonding technology (LT-HBT). Good manufacturability of the hetero-oriented Ge platform was verified with XRD 2?-? scan, Raman spectra, Selected Area Diffraction (SAD), and Converged Beam Electron Diffraction (CBED). Balanced device performance in terms of C-V, ID-VG, ID-VD and ?c for Ge (111) nFET and Ge (100) pFET was achieved, leading to better VTCs and voltage gains.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages399-400
Number of pages2
ISBN (Electronic)9781665497725
DOIs
StatePublished - 2022
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 12 Jun 202217 Jun 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period12/06/2217/06/22

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