First Demonstration of GAA Monolayer-MoS2Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

Yun Yan Chung; Bo Jhih Chou; Chen Feng Hsu; Wei Sheng Yun; Ming Yang Li; Sheng Kai Su; Yu Tsung Liao; Meng Chien Lee; Guo Wei Huang; San Lin Liew; Yun Yang Shen; Wen Hao Chang; Chien Wei Chen; Chi Chung Kei; Han Wang; H. S. Philip Wong; T. Y. Lee; Chao Hsin Chien; Chao Ching Cheng; Iuliana P. Radu

doi:10.1109/IEDM45625.2022.10019563

First Demonstration of GAA Monolayer-MoS₂Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

Yun Yan Chung^*, Bo Jhih Chou, Chen Feng Hsu, Wei Sheng Yun, Ming Yang Li, Sheng Kai Su, Yu Tsung Liao, Meng Chien Lee, Guo Wei Huang, San Lin Liew, Yun Yang Shen, Wen Hao Chang, Chien Wei Chen, Chi Chung Kei, Han Wang, H. S. Philip Wong, T. Y. Lee, Chao Hsin Chien, Chao Ching Cheng, Iuliana P. Radu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.

Original language	English
Title of host publication	2022 International Electron Devices Meeting, IEDM 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3451-3454
Number of pages	4
ISBN (Electronic)	9781665489591
DOIs	https://doi.org/10.1109/IEDM45625.2022.10019563
State	Published - 2022
Event	2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States Duration: 3 Dec 2022 → 7 Dec 2022

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2022-December
ISSN (Print)	0163-1918

Conference

Conference	2022 International Electron Devices Meeting, IEDM 2022
Country/Territory	United States
City	San Francisco
Period	3/12/22 → 7/12/22

Access to Document

10.1109/IEDM45625.2022.10019563

Cite this

Chung, Y. Y., Chou, B. J., Hsu, C. F., Yun, W. S., Li, M. Y., Su, S. K., Liao, Y. T., Lee, M. C., Huang, G. W., Liew, S. L., Shen, Y. Y., Chang, W. H., Chen, C. W., Kei, C. C., Wang, H., Philip Wong, H. S., Lee, T. Y., Chien, C. H., Cheng, C. C., & Radu, I. P. (2022). First Demonstration of GAA Monolayer-MoS₂Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length. In 2022 International Electron Devices Meeting, IEDM 2022 (pp. 3451-3454). (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45625.2022.10019563

@inproceedings{0d571dcdb8da43b98a613d32f0712698,

title = "First Demonstration of GAA Monolayer-MoS2Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length",

abstract = "This work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.",

author = "Chung, {Yun Yan} and Chou, {Bo Jhih} and Hsu, {Chen Feng} and Yun, {Wei Sheng} and Li, {Ming Yang} and Su, {Sheng Kai} and Liao, {Yu Tsung} and Lee, {Meng Chien} and Huang, {Guo Wei} and Liew, {San Lin} and Shen, {Yun Yang} and Chang, {Wen Hao} and Chen, {Chien Wei} and Kei, {Chi Chung} and Han Wang and {Philip Wong}, {H. S.} and Lee, {T. Y.} and Chien, {Chao Hsin} and Cheng, {Chao Ching} and Radu, {Iuliana P.}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",

year = "2022",

doi = "10.1109/IEDM45625.2022.10019563",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "3451--3454",

booktitle = "2022 International Electron Devices Meeting, IEDM 2022",

address = "United States",

}

Chung, YY, Chou, BJ, Hsu, CF, Yun, WS, Li, MY, Su, SK, Liao, YT, Lee, MC, Huang, GW, Liew, SL, Shen, YY, Chang, WH, Chen, CW, Kei, CC, Wang, H, Philip Wong, HS, Lee, TY, Chien, CH, Cheng, CC & Radu, IP 2022, First Demonstration of GAA Monolayer-MoS₂Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length. in 2022 International Electron Devices Meeting, IEDM 2022. Technical Digest - International Electron Devices Meeting, IEDM, vol. 2022-December, Institute of Electrical and Electronics Engineers Inc., pp. 3451-3454, 2022 International Electron Devices Meeting, IEDM 2022, San Francisco, United States, 3/12/22. https://doi.org/10.1109/IEDM45625.2022.10019563

First Demonstration of GAA Monolayer-MoS₂Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length. / Chung, Yun Yan; Chou, Bo Jhih; Hsu, Chen Feng et al.
2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 3451-3454 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - First Demonstration of GAA Monolayer-MoS2Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

AU - Chung, Yun Yan

AU - Chou, Bo Jhih

AU - Hsu, Chen Feng

AU - Yun, Wei Sheng

AU - Li, Ming Yang

AU - Su, Sheng Kai

AU - Liao, Yu Tsung

AU - Lee, Meng Chien

AU - Huang, Guo Wei

AU - Liew, San Lin

AU - Shen, Yun Yang

AU - Chang, Wen Hao

AU - Chen, Chien Wei

AU - Kei, Chi Chung

AU - Wang, Han

AU - Philip Wong, H. S.

AU - Lee, T. Y.

AU - Chien, Chao Hsin

AU - Cheng, Chao Ching

AU - Radu, Iuliana P.

PY - 2022

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N2 - This work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.

AB - This work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.

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U2 - 10.1109/IEDM45625.2022.10019563

DO - 10.1109/IEDM45625.2022.10019563

M3 - Conference contribution

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

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BT - 2022 International Electron Devices Meeting, IEDM 2022

PB - Institute of Electrical and Electronics Engineers Inc.

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Chung YY, Chou BJ, Hsu CF, Yun WS, Li MY, Su SK et al. First Demonstration of GAA Monolayer-MoS₂Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length. In 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 3451-3454. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45625.2022.10019563