Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation

Ming Hung Wu, Horng-Chih Lin*, Pei-Wen Li

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


We report the design and fabrication of ZnO thin-film transistors (TFTs) configured with designed gate-to-drain (G/D)-offset structures and an auxiliary gate (AG) in a film-profile engineering (FPE) approach for back-end-of-line high-voltage (HV) operation. The breakdown voltage (V BD) of fabricated FPE TFTs is significantly enhanced from 23 to 90 V by changing the G/D-offset length from-0.3 to 0.5 μm, whereas there is a corresponding decrease in the on-state current and transconductance (G m). To boost the on-state current, an AG biased in the range of 0-5 V is designed to effectively modulate the resistivity of the G/D-offset region and improve G m by a factor of 2 while keeping V BD of 65-70 V nearly unchanged. Output characteristics with drain voltage as high as 60 V have been demonstrated, evidencing the promising potential of the ZnO TFTs for HV device applications.

Original languageEnglish
Article number066502
JournalJapanese journal of applied physics
Issue number6
StatePublished - 1 Jun 2019


Dive into the research topics of 'Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation'. Together they form a unique fingerprint.

Cite this