Field Plate and Package Optimization for GaN Devices and Systems

Sheng Hsi Hung, Tz Wun Wang, Chien Wei Cho, Po Jui Chiu, Chi Yu Chen, Ke Horng Chen, Kuo Lin Zheng, Chih Chen Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

To improve GaN-based system performance, this work demonstrates the 650V GaN field plate (FP) design and the optimized integrated circuit (IC) package. The source FP length is suggested to be longer but less than three times the split high FP (HFP). The connection of the split FP and the 1ST FP to source FP can reduce Coss. Longer 1ST FP and shorter Gap design enhance the Miller ratio and suppress the ringing effect in case of switching. The asynchronous boost converter can be implemented with minimal parasitics and double-sided cooling in a proposed 3D IC package.

Original languageEnglish
Title of host publication2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350361469
DOIs
StatePublished - 2024
Event2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States
Duration: 16 Jun 202420 Jun 2024

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/TerritoryUnited States
CityHonolulu
Period16/06/2420/06/24

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