Fault models for embedded-DRAM macros

Chia-Tso Chao; Hao Yu Yang; Rei Fu Huang; Shih Chin Lin; G. Yu Chin

doi:10.1145/1629911.1630097

Fault models for embedded-DRAM macros

Chia-Tso Chao, Hao Yu Yang, Rei Fu Huang, Shih Chin Lin, G. Yu Chin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.

Original language	English
Title of host publication	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	714-719
Number of pages	6
ISBN (Print)	9781605584973
DOIs	https://doi.org/10.1145/1629911.1630097
State	Published - 2009
Event	2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States Duration: 26 Jul 2009 → 31 Jul 2009

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Country/Territory	United States
City	San Francisco, CA
Period	26/07/09 → 31/07/09

Keywords

Embedded DRAM
Memory testing

Access to Document

10.1145/1629911.1630097

Cite this

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title = "Fault models for embedded-DRAM macros",

abstract = "In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.",

keywords = "Embedded DRAM, Memory testing",

author = "Chia-Tso Chao and Yang, {Hao Yu} and Huang, {Rei Fu} and Lin, {Shih Chin} and Chin, {G. Yu}",

year = "2009",

doi = "10.1145/1629911.1630097",

language = "English",

isbn = "9781605584973",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "714--719",

booktitle = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009",

address = "美國",

note = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009 ; Conference date: 26-07-2009 Through 31-07-2009",

}

Chao, C-T, Yang, HY, Huang, RF, Lin, SC & Chin, GY 2009, Fault models for embedded-DRAM macros. in 2009 46th ACM/IEEE Design Automation Conference, DAC 2009., 5227104, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 714-719, 2009 46th ACM/IEEE Design Automation Conference, DAC 2009, San Francisco, CA, United States, 26/07/09. https://doi.org/10.1145/1629911.1630097

Fault models for embedded-DRAM macros. / Chao, Chia-Tso; Yang, Hao Yu; Huang, Rei Fu et al.
2009 46th ACM/IEEE Design Automation Conference, DAC 2009. Institute of Electrical and Electronics Engineers Inc., 2009. p. 714-719 5227104 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fault models for embedded-DRAM macros

AU - Chao, Chia-Tso

AU - Yang, Hao Yu

AU - Huang, Rei Fu

AU - Lin, Shih Chin

AU - Chin, G. Yu

PY - 2009

Y1 - 2009

N2 - In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.

AB - In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.

KW - Embedded DRAM

KW - Memory testing

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U2 - 10.1145/1629911.1630097

DO - 10.1145/1629911.1630097

M3 - Conference contribution

AN - SCOPUS:70350708317

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T3 - Proceedings - Design Automation Conference

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EP - 719

BT - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009

Y2 - 26 July 2009 through 31 July 2009

ER -

Fault models for embedded-DRAM macros

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Keywords

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