Fault models for embedded-DRAM macros

Chia-Tso Chao, Hao Yu Yang, Rei Fu Huang, Shih Chin Lin, G. Yu Chin

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    10 Scopus citations


    In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.

    Original languageEnglish
    Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Number of pages6
    ISBN (Print)9781605584973
    StatePublished - 2009
    Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
    Duration: 26 Jul 200931 Jul 2009

    Publication series

    NameProceedings - Design Automation Conference
    ISSN (Print)0738-100X


    Conference2009 46th ACM/IEEE Design Automation Conference, DAC 2009
    Country/TerritoryUnited States
    CitySan Francisco, CA


    • Embedded DRAM
    • Memory testing


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