Fast thermal aware placement with accurate thermal analysis based on green function

Sean Shih Ying Liu; Ren Guo Luo; Suradeth Aroonsantidecha; Ching Yu Chin; Hung-Ming Chen

doi:10.1109/TVLSI.2013.2268582

Fast thermal aware placement with accurate thermal analysis based on green function

Sean Shih Ying Liu, Ren Guo Luo, Suradeth Aroonsantidecha, Ching Yu Chin, Hung-Ming Chen

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

Original language	English
Article number	6553166
Pages (from-to)	1404-1415
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	22
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2013.2268582
State	Published - 1 Jan 2014

Keywords

Design for manufacture
design for quality
design methodology
electronic design automation
logic design
placement
temperature control
thermal analysis.

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10.1109/TVLSI.2013.2268582

Cite this

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title = "Fast thermal aware placement with accurate thermal analysis based on green function",

abstract = "In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.",

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AB - In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

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Fast thermal aware placement with accurate thermal analysis based on green function

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