A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90° phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3° at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).
- DDR controller
- Fast lock