Fast analog layout prototyping for nanometer design migration

Yi Peng Weng*, Hung-Ming Chen, Tung Chieh Chen, Po Cheng Pan, Chien Hung Chen, Wei-Zen Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

27 Scopus citations

Abstract

This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.

Original languageEnglish
Title of host publication2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Pages517-522
Number of pages6
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011 - San Jose, CA, United States
Duration: 7 Nov 201110 Nov 2011

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Country/TerritoryUnited States
CitySan Jose, CA
Period7/11/1110/11/11

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