Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Chia Tsen Dai; Po Yen Chiu; Ming-Dou Ker; Fu Yi Tsai; Yan Hua Peng; Chia Ku Tsai

doi:10.1109/IPFA.2012.6306283

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Chia Tsen Dai^*, Po Yen Chiu, Ming-Dou Ker, Fu Yi Tsai, Yan Hua Peng, Chia Ku Tsai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

Original language	English
Title of host publication	2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
DOIs	https://doi.org/10.1109/IPFA.2012.6306283
State	Published - 19 Nov 2012
Event	2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 - Singapore, Singapore Duration: 2 Jul 2012 → 6 Jul 2012

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
Country/Territory	Singapore
City	Singapore
Period	2/07/12 → 6/07/12

Access to Document

10.1109/IPFA.2012.6306283

Cite this

Dai, C. T., Chiu, P. Y., Ker, M-D., Tsai, F. Y., Peng, Y. H., & Tsai, C. K. (2012). Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process. In 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 [6306283] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2012.6306283

Dai, Chia Tsen ; Chiu, Po Yen ; Ker, Ming-Dou et al. / Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process. 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012. 2012. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{4012143b05a44e46a1db809d18f54fd0,

title = "Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process",

abstract = "The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.",

author = "Dai, {Chia Tsen} and Chiu, {Po Yen} and Ming-Dou Ker and Tsai, {Fu Yi} and Peng, {Yan Hua} and Tsai, {Chia Ku}",

year = "2012",

month = nov,

day = "19",

doi = "10.1109/IPFA.2012.6306283",

language = "English",

isbn = "9781467309806",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012",

note = "2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 ; Conference date: 02-07-2012 Through 06-07-2012",

}

Dai, CT, Chiu, PY, Ker, M-D, Tsai, FY, Peng, YH & Tsai, CK 2012, Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process. in 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012., 6306283, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012, Singapore, Singapore, 2/07/12. https://doi.org/10.1109/IPFA.2012.6306283

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process. / Dai, Chia Tsen; Chiu, Po Yen; Ker, Ming-Dou et al.
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012. 2012. 6306283 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

AU - Dai, Chia Tsen

AU - Chiu, Po Yen

AU - Ker, Ming-Dou

AU - Tsai, Fu Yi

AU - Peng, Yan Hua

AU - Tsai, Chia Ku

PY - 2012/11/19

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N2 - The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

AB - The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

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Dai CT, Chiu PY, Ker M-D, Tsai FY, Peng YH, Tsai CK. Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process. In 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012. 2012. 6306283. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2012.6306283

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

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