Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Keyphrases

• Inverter 100%
• Junctionless FET 100%
• Complementary Field-effect Transistors 100%
• Vertically Stacked Nanosheet 100%
• Dry Etching 40%
• Nanosheets 40%
• CMOS Inverter 40%
• Channel Width 40%
• Voltage Transfer Characteristics 40%
• Nanosheet Structure 40%
• NSFET 40%
• On-state Current 20%
• 3D IC 20%
• NWFET 20%
• Ion Implantation 20%
• Layout Area 20%
• Conventional CMOS 20%
• Threshold Voltage 20%
• System on Panel 20%
• Wet Etching 20%
• Wetting-drying 20%
• Channel Thickness 20%
• Wet Etch Process 20%
• Layer Behavior 20%
• N-channel MOSFET 20%
• Channel Layer 20%
• NFET 20%
• P-channel MOSFET 20%
• Single Nanowire 20%
• Inverter-based 20%
• Asymmetric Behavior 20%
• Systematic Behavior 20%
• Channel Layer Thickness 20%
• Inverter Layout 20%

Engineering

• Field-Effect Transistor 100%
• Nanosheet 100%
• Inverter 100%
• Metal-Oxide-Semiconductor Field-Effect Transistor 28%
• Dry Etching 28%
• Layer Thickness 14%
• Ion Implantation 14%
• Etching Process 14%
• Channel Layer 14%
• Nanowire 14%

Material Science

• Field Effect Transistor 100%
• Nanosheet 100%
• Dry Etching 28%
• Metal-Oxide-Semiconductor Field-Effect Transistor 28%
• Wet Etching 28%
• Nanowire 14%
• Ion Implantation 14%