Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure

Rong Jhe Lyu; Horng-Chih Lin; Tiao Yuan Huang

doi:10.1109/VLSI-TSA.2015.7117553

Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure

Rong Jhe Lyu, Horng-Chih Lin, Tiao Yuan Huang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.

Original language	English
Title of host publication	2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479973750
DOIs	https://doi.org/10.1109/VLSI-TSA.2015.7117553
State	Published - 3 Jun 2015
Event	2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume	2015-June
ISSN (Print)	1930-8868

Conference

Conference	2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
Country/Territory	Taiwan
City	Hsinchu
Period	27/04/15 → 29/04/15

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10.1109/VLSI-TSA.2015.7117553

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Lyu, R. J., Lin, H.-C., & Huang, T. Y. (2015). Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure. In 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 Article 7117553 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; Vol. 2015-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2015.7117553

Lyu, Rong Jhe ; Lin, Horng-Chih ; Huang, Tiao Yuan. / Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure. 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

@inproceedings{8948dc6aae8a464f93b84772155e042e,

title = "Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure",

abstract = "We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.",

author = "Lyu, {Rong Jhe} and Horng-Chih Lin and Huang, {Tiao Yuan}",

year = "2015",

month = jun,

day = "3",

doi = "10.1109/VLSI-TSA.2015.7117553",

language = "English",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015",

address = "美國",

note = "2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

}

Lyu, RJ, Lin, H-C & Huang, TY 2015, Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure. in 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015., 7117553, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, vol. 2015-June, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-TSA.2015.7117553

Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure. / Lyu, Rong Jhe; Lin, Horng-Chih; Huang, Tiao Yuan.
2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7117553 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; Vol. 2015-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure

AU - Lyu, Rong Jhe

AU - Lin, Horng-Chih

AU - Huang, Tiao Yuan

PY - 2015/6/3

Y1 - 2015/6/3

N2 - We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.

AB - We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.

UR - http://www.scopus.com/inward/record.url?scp=84940779537&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2015.7117553

DO - 10.1109/VLSI-TSA.2015.7117553

M3 - Conference contribution

AN - SCOPUS:84940779537

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

BT - 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015

Y2 - 27 April 2015 through 29 April 2015

ER -

Lyu RJ, Lin HC, Huang TY. Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure. In 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7117553. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). doi: 10.1109/VLSI-TSA.2015.7117553

Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure

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