Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

Chen Chen Yang; Yung Chen Chen; Horng-Chih Lin; Ruey Dar Chang; Pei-Wen Li; Tiao Yuan Huang

doi:10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

Chen Chen Yang, Yung Chen Chen, Horng-Chih Lin, Ruey Dar Chang, Pei-Wen Li, Tiao Yuan Huang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (G_m). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

Original language	American English
Title of host publication	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	64-65
Number of pages	2
ISBN (Electronic)	9781509007264
DOIs	https://doi.org/10.1109/SNW.2016.7577987
State	Published - 27 Sep 2016
Event	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States Duration: 12 Jun 2016 → 13 Jun 2016

Publication series

Name	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Conference

Conference	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
Country/Territory	United States
City	Honolulu
Period	12/06/16 → 13/06/16

Keywords

MOSFET
Logic gates
Radio frequency

Access to Document

10.1109/SNW.2016.7577987

Cite this

Yang, C. C., Chen, Y. C., Lin, H.-C., Chang, R. D., Li, P.-W., & Huang, T. Y. (2016). Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. In 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016 (pp. 64-65). Article 7577987 (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW.2016.7577987

@inproceedings{a881193fb4874487a2c310973409f2bf,

title = "Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors",

abstract = "Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.",

keywords = "MOSFET, Logic gates, Radio frequency",

author = "Yang, {Chen Chen} and Chen, {Yung Chen} and Horng-Chih Lin and Chang, {Ruey Dar} and Pei-Wen Li and Huang, {Tiao Yuan}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 ; Conference date: 12-06-2016 Through 13-06-2016",

year = "2016",

month = sep,

day = "27",

doi = "10.1109/SNW.2016.7577987",

language = "American English",

series = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "64--65",

booktitle = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

address = "United States",

}

Yang, CC, Chen, YC, Lin, H-C, Chang, RD, Li, P-W & Huang, TY 2016, Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. in 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016., 7577987, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016, Institute of Electrical and Electronics Engineers Inc., pp. 64-65, 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016, Honolulu, United States, 12/06/16. https://doi.org/10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. / Yang, Chen Chen; Chen, Yung Chen; Lin, Horng-Chih et al.
2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 64-65 7577987 (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

AU - Yang, Chen Chen

AU - Chen, Yung Chen

AU - Lin, Horng-Chih

AU - Chang, Ruey Dar

AU - Li, Pei-Wen

AU - Huang, Tiao Yuan

PY - 2016/9/27

Y1 - 2016/9/27

N2 - Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

AB - Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

KW - MOSFET

KW - Logic gates

KW - Radio frequency

UR - http://www.scopus.com/inward/record.url?scp=84994761593&partnerID=8YFLogxK

U2 - 10.1109/SNW.2016.7577987

DO - 10.1109/SNW.2016.7577987

M3 - Conference contribution

AN - SCOPUS:84994761593

T3 - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

SP - 64

EP - 65

BT - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016

Y2 - 12 June 2016 through 13 June 2016

ER -

Yang CC, Chen YC, Lin HC, Chang RD, Li PW, Huang TY. Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. In 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 64-65. 7577987. (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016). doi: 10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this