TY - GEN
T1 - Fabrication and characterization of Pi-gate poly-Si junctionless and inversion mode Fin-FETs for 3-D IC applications
AU - Hsieh, Don Ru
AU - Lin, Jer Yi
AU - Kuo, Po Yi
AU - Chao, Tien-Sheng
PY - 2016/9/27
Y1 - 2016/9/27
N2 - In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) ∼ 68 mV/dec., steep average subthreshold swing (A.S.S.) ∼ 73 mV/dec., smaller drain induced barrier lowing (DIBL) ∼ 9 mV/V, and higher Ion/Ioff ratio ∼ 1.1 × 108 (VD = 1 V).
AB - In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) ∼ 68 mV/dec., steep average subthreshold swing (A.S.S.) ∼ 73 mV/dec., smaller drain induced barrier lowing (DIBL) ∼ 9 mV/V, and higher Ion/Ioff ratio ∼ 1.1 × 108 (VD = 1 V).
UR - http://www.scopus.com/inward/record.url?scp=84994797323&partnerID=8YFLogxK
U2 - 10.1109/SNW.2016.7578007
DO - 10.1109/SNW.2016.7578007
M3 - Conference contribution
AN - SCOPUS:84994797323
T3 - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
SP - 110
EP - 111
BT - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
Y2 - 12 June 2016 through 13 June 2016
ER -