TY - GEN
T1 - Exploration and evaluation of TCAM with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications
AU - Tu, Meng Hsuan
AU - Chen, Yin Nien
AU - Su, Pin
AU - Chuang, Ching Te
PY - 2017/6/7
Y1 - 2017/6/7
N2 - In this paper, we investigate the hybrid TFET-FinFET implementation of ternary content addressable memory (TCAM) and compare the search time, power and energy with all FinFET and all TFET implementations in near-threshold region using atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The TCAM utilizes a don't-care-based ripple search line (SL) to improve the search performance and power. In the hybrid design, TFETs are used for comparison circuit to improve the performance and energy of serially connected match line (ML) at low voltage, while FinFETs are used for the rest of the circuit for better cell stability, switching power and leakage power.
AB - In this paper, we investigate the hybrid TFET-FinFET implementation of ternary content addressable memory (TCAM) and compare the search time, power and energy with all FinFET and all TFET implementations in near-threshold region using atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The TCAM utilizes a don't-care-based ripple search line (SL) to improve the search performance and power. In the hybrid design, TFETs are used for comparison circuit to improve the performance and energy of serially connected match line (ML) at low voltage, while FinFETs are used for the rest of the circuit for better cell stability, switching power and leakage power.
UR - http://www.scopus.com/inward/record.url?scp=85023162547&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2017.7942494
DO - 10.1109/VLSI-TSA.2017.7942494
M3 - Conference contribution
AN - SCOPUS:85023162547
T3 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
BT - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Y2 - 24 April 2017 through 27 April 2017
ER -