Exploiting Binary Equilibrium for Efficient LDPC Decoding in 3D NAND Flash

Hsiang Sen Hsu, Li Pin Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

3D NAND flash is prone to bit errors due to severe charge leakage. Modern SSDs adopt LDPC for bit error management, but LDPC can incur a high read latency through iterative adjustment to the reference voltage. Bit scrambling helps reduce inter-cell interference, and with it, ones and zeros equally contribute to raw data. We observed that as bit errors develop, the 0-bit ratio in raw data deviates from 50%. Inspired by this property, we propose a method for fast adjustment to the reference voltage, involving a placement step and a fine-tuning step. Our method uses only a few hundreds of bytes of RAM but improves the average read latency upon existing methods by up to 24%.

Original languageEnglish
Title of host publicationProceedings - 2022 IEEE 28th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages113-119
Number of pages7
ISBN (Electronic)9781665453448
DOIs
StatePublished - 2022
Event28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2022 - Taipei, Taiwan
Duration: 23 Aug 202225 Aug 2022

Publication series

NameProceedings - 2022 IEEE 28th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2022

Conference

Conference28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2022
Country/TerritoryTaiwan
CityTaipei
Period23/08/2225/08/22

Keywords

  • Flash Reliability
  • LDPC
  • NAND Flash
  • Read Latency
  • Solid-State Disks

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