Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

Sheng Fu Hsu; Ming-Dou Ker; Geeng Lih Lin; Yeh Ning Jou

doi:10.1109/RELPHY.2006.251206

Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

Sheng Fu Hsu^*, Ming-Dou Ker, Geeng Lih Lin, Yeh Ning Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.

Original language	English
Title of host publication	2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
Pages	140-144
Number of pages	5
DOIs	https://doi.org/10.1109/RELPHY.2006.251206
State	Published - 1 Dec 2006
Event	44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States Duration: 26 Mar 2006 → 30 Mar 2006

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
Country/Territory	United States
City	San Jose, CA
Period	26/03/06 → 30/03/06

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10.1109/RELPHY.2006.251206

Cite this

Hsu, S. F., Ker, M.-D., Lin, G. L., & Jou, Y. N. (2006). Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process. In 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual (pp. 140-144). Article 4017147 (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2006.251206

@inproceedings{470d1ab943b34155b8d0ac9aabcce861,

title = "Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process",

abstract = "The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.",

author = "Hsu, {Sheng Fu} and Ming-Dou Ker and Lin, {Geeng Lih} and Jou, {Yeh Ning}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/RELPHY.2006.251206",

language = "English",

isbn = "0780394992",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "140--144",

booktitle = "2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual",

note = "44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 ; Conference date: 26-03-2006 Through 30-03-2006",

}

Hsu, SF, Ker, M-D, Lin, GL & Jou, YN 2006, Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process. in 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual., 4017147, IEEE International Reliability Physics Symposium Proceedings, pp. 140-144, 44th Annual IEEE International Reliability Physics Symposium, IRPS 2006, San Jose, CA, United States, 26/03/06. https://doi.org/10.1109/RELPHY.2006.251206

Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process. / Hsu, Sheng Fu; Ker, Ming-Dou; Lin, Geeng Lih et al.
2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual. 2006. p. 140-144 4017147 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

AU - Hsu, Sheng Fu

AU - Ker, Ming-Dou

AU - Lin, Geeng Lih

AU - Jou, Yeh Ning

PY - 2006/12/1

Y1 - 2006/12/1

N2 - The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.

AB - The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.

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U2 - 10.1109/RELPHY.2006.251206

DO - 10.1109/RELPHY.2006.251206

M3 - Conference contribution

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SN - 0780394992

SN - 0780394984

SN - 9780780394988

T3 - IEEE International Reliability Physics Symposium Proceedings

SP - 140

EP - 144

BT - 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual

T2 - 44th Annual IEEE International Reliability Physics Symposium, IRPS 2006

Y2 - 26 March 2006 through 30 March 2006

ER -

Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

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