Expandable MDC-based FFT architecture and its generator for high-performance applications

Bu Ching Lin; Yu Hsiang Wang; Juinn-Dar Huang; Jing Yang Jou

doi:10.1109/SOCC.2010.5784750

Expandable MDC-based FFT architecture and its generator for high-performance applications

Bu Ching Lin^*, Yu Hsiang Wang, Juinn-Dar Huang, Jing Yang Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Fast Fourier Transform (FFT) cores are extensively used in digital signal processing (DSP) applications like communication systems. Many pipelined FFT architectures optimized for different objectives have been proposed in past few decades. Though a fixed pipelined FFT architecture can generally provide good throughput at reasonable hardware cost, it may still fail to meet the performance demand for throughput-hungry design cases. In this paper, we propose an expandable MDC-based FFT architecture as well as the corresponding hardware design generator, which is capable of automatically producing an FFT core under a given throughput constraint. The experimental results show that the proposed methodology can generate smaller and power-efficient implementations than the existing foldable MDC-based FFT architecture.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	188-192
Number of pages	5
DOIs	https://doi.org/10.1109/SOCC.2010.5784750
State	Published - 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

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10.1109/SOCC.2010.5784750

Cite this

@inproceedings{0bac9da75571488492d209ab66743a98,

title = "Expandable MDC-based FFT architecture and its generator for high-performance applications",

abstract = "Fast Fourier Transform (FFT) cores are extensively used in digital signal processing (DSP) applications like communication systems. Many pipelined FFT architectures optimized for different objectives have been proposed in past few decades. Though a fixed pipelined FFT architecture can generally provide good throughput at reasonable hardware cost, it may still fail to meet the performance demand for throughput-hungry design cases. In this paper, we propose an expandable MDC-based FFT architecture as well as the corresponding hardware design generator, which is capable of automatically producing an FFT core under a given throughput constraint. The experimental results show that the proposed methodology can generate smaller and power-efficient implementations than the existing foldable MDC-based FFT architecture.",

author = "Lin, {Bu Ching} and Wang, {Yu Hsiang} and Juinn-Dar Huang and Jou, {Jing Yang}",

year = "2010",

doi = "10.1109/SOCC.2010.5784750",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "188--192",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Lin, BC, Wang, YH, Huang, J-D & Jou, JY 2010, Expandable MDC-based FFT architecture and its generator for high-performance applications. in Proceedings - IEEE International SOC Conference, SOCC 2010., 5784750, Proceedings - IEEE International SOC Conference, SOCC 2010, pp. 188-192, 23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, United States, 27/09/10. https://doi.org/10.1109/SOCC.2010.5784750

Expandable MDC-based FFT architecture and its generator for high-performance applications. / Lin, Bu Ching; Wang, Yu Hsiang; Huang, Juinn-Dar et al.
Proceedings - IEEE International SOC Conference, SOCC 2010. 2010. p. 188-192 5784750 (Proceedings - IEEE International SOC Conference, SOCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Expandable MDC-based FFT architecture and its generator for high-performance applications

AU - Lin, Bu Ching

AU - Wang, Yu Hsiang

AU - Huang, Juinn-Dar

AU - Jou, Jing Yang

PY - 2010

Y1 - 2010

N2 - Fast Fourier Transform (FFT) cores are extensively used in digital signal processing (DSP) applications like communication systems. Many pipelined FFT architectures optimized for different objectives have been proposed in past few decades. Though a fixed pipelined FFT architecture can generally provide good throughput at reasonable hardware cost, it may still fail to meet the performance demand for throughput-hungry design cases. In this paper, we propose an expandable MDC-based FFT architecture as well as the corresponding hardware design generator, which is capable of automatically producing an FFT core under a given throughput constraint. The experimental results show that the proposed methodology can generate smaller and power-efficient implementations than the existing foldable MDC-based FFT architecture.

AB - Fast Fourier Transform (FFT) cores are extensively used in digital signal processing (DSP) applications like communication systems. Many pipelined FFT architectures optimized for different objectives have been proposed in past few decades. Though a fixed pipelined FFT architecture can generally provide good throughput at reasonable hardware cost, it may still fail to meet the performance demand for throughput-hungry design cases. In this paper, we propose an expandable MDC-based FFT architecture as well as the corresponding hardware design generator, which is capable of automatically producing an FFT core under a given throughput constraint. The experimental results show that the proposed methodology can generate smaller and power-efficient implementations than the existing foldable MDC-based FFT architecture.

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M3 - Conference contribution

AN - SCOPUS:79960739906

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

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BT - Proceedings - IEEE International SOC Conference, SOCC 2010

T2 - 23rd IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

Expandable MDC-based FFT architecture and its generator for high-performance applications

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