TY - JOUR
T1 - Event-driven incremental timing fault simulator
AU - Jou, Shyh-Jye
AU - Chiou, S. H.
AU - Tao, Y. S.
AU - Shen, W. Z.
PY - 1993/1/1
Y1 - 1993/1/1
N2 - An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multi-processor system.
AB - An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multi-processor system.
UR - http://www.scopus.com/inward/record.url?scp=0027540360&partnerID=8YFLogxK
U2 - 10.1049/ip-g-2.1993.0007
DO - 10.1049/ip-g-2.1993.0007
M3 - Article
AN - SCOPUS:0027540360
SN - 0956-3768
VL - 140
SP - 45
EP - 54
JO - IEE Proceedings, Part G: Circuits, Devices and Systems
JF - IEE Proceedings, Part G: Circuits, Devices and Systems
IS - 1
ER -