Event-driven incremental timing fault simulator

Shyh-Jye Jou*, S. H. Chiou, Y. S. Tao, W. Z. Shen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multi-processor system.

Original languageEnglish
Pages (from-to)45-54
Number of pages10
JournalIEE Proceedings, Part G: Circuits, Devices and Systems
Issue number1
StatePublished - 1 Jan 1993


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