Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

Wei Xiang You; Pin Su; Chen-Ming Hu

doi:10.1109/TED.2019.2898445

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

Wei Xiang You
, Pin Su^*
, Chen-Ming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

42 Scopus citations

Abstract

This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V_ds-dependence of threshold voltage (V_T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V_DD.

Original language	English
Article number	8653878
Pages (from-to)	2004-2009
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	4
DOIs	https://doi.org/10.1109/TED.2019.2898445
State	Published - Apr 2019

Keywords

Dynamic adder
FinFET
Landau-Khalatnikov (L-K) equation
NCFET
logic circuits
metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance field-effect transistor (NCFET)
pass-transistor logic (PTL)

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10.1109/TED.2019.2898445

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@article{f107d068a3e04696b6a444bcf9e1a8cd,

title = "Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits",

abstract = "This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD.",

keywords = "Dynamic adder, FinFET, Landau-Khalatnikov (L-K) equation, NCFET, logic circuits, metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance field-effect transistor (NCFET), pass-transistor logic (PTL)",

author = "You, \{Wei Xiang\} and Pin Su and Chen-Ming Hu",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.",

year = "2019",

month = apr,

doi = "10.1109/TED.2019.2898445",

language = "English",

volume = "66",

pages = "2004--2009",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

AU - You, Wei Xiang

AU - Su, Pin

AU - Hu, Chen-Ming

PY - 2019/4

Y1 - 2019/4

N2 - This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD.

AB - This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD.

KW - Dynamic adder

KW - FinFET

KW - Landau-Khalatnikov (L-K) equation

KW - NCFET

KW - logic circuits

KW - metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance field-effect transistor (NCFET)

KW - pass-transistor logic (PTL)

UR - https://www.scopus.com/pages/publications/85063271196

U2 - 10.1109/TED.2019.2898445

DO - 10.1109/TED.2019.2898445

M3 - Article

AN - SCOPUS:85063271196

SN - 0018-9383

VL - 66

SP - 2004

EP - 2009

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 4

M1 - 8653878

ER -

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

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Keywords

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