@inproceedings{2d1e0a53823443a8aab35c29c3965ce3,
title = "Evaluation of NC-FinFET based subsystem-level logic circuits using SPICE simulation",
abstract = "This work examines the metal-ferroelectric-insulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse Vds-dependency of threshold voltage (VT), also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD.",
keywords = "Dynamic adder, FinFET, Landau-Khalatnikov (L-K) equation, Logic circuits, MFIS-type NCFET, Negative-capacitance field-effect transistor (NCFET), PTL",
author = "You, {Wei Xiang} and Pin Su and Chen-Ming Hu",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 ; Conference date: 15-10-2018 Through 18-10-2018",
year = "2018",
month = jul,
day = "2",
doi = "10.1109/S3S.2018.8640175",
language = "English",
series = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
address = "美國",
}