Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications

Kuei Yang Tseng; Wei Xiang You; Pin Su

doi:10.1109/VLSI-TSA.2019.8804704

Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications

Kuei Yang Tseng, Wei Xiang You, Pin Su

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-Type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for \mathrm{V}-{\mathrm{DD}} =0.2\mathrm{V} due to the existence of hysteresis loop in write curve during write operation. By using write-Assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.

Original language	English
Title of host publication	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728109428
DOIs	https://doi.org/10.1109/VLSI-TSA.2019.8804704
State	Published - Apr 2019
Event	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan Duration: 22 Apr 2019 → 25 Apr 2019

Publication series

Name	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/19 → 25/04/19

Access to Document

10.1109/VLSI-TSA.2019.8804704

Cite this

Tseng, K. Y., You, W. X., & Su, P. (2019). Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 Article 8804704 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804704

@inproceedings{fc296b529f914ae38600d7ff23ac0fe8,

title = "Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications",

abstract = "In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-Type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for \mathrm{V}-{\mathrm{DD}} =0.2\mathrm{V} due to the existence of hysteresis loop in write curve during write operation. By using write-Assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.",

author = "Tseng, {Kuei Yang} and You, {Wei Xiang} and Pin Su",

year = "2019",

month = apr,

doi = "10.1109/VLSI-TSA.2019.8804704",

language = "English",

series = "2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019",

address = "美國",

note = "2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

}

Tseng, KY, You, WX & Su, P 2019, Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications. in 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019., 8804704, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Hsinchu, Taiwan, 22/04/19. https://doi.org/10.1109/VLSI-TSA.2019.8804704

Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications. / Tseng, Kuei Yang; You, Wei Xiang; Su, Pin.
2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8804704 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications

AU - Tseng, Kuei Yang

AU - You, Wei Xiang

AU - Su, Pin

PY - 2019/4

Y1 - 2019/4

N2 - In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-Type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for \mathrm{V}-{\mathrm{DD}} =0.2\mathrm{V} due to the existence of hysteresis loop in write curve during write operation. By using write-Assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.

AB - In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-Type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for \mathrm{V}-{\mathrm{DD}} =0.2\mathrm{V} due to the existence of hysteresis loop in write curve during write operation. By using write-Assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.

UR - http://www.scopus.com/inward/record.url?scp=85072127138&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2019.8804704

DO - 10.1109/VLSI-TSA.2019.8804704

M3 - Conference contribution

AN - SCOPUS:85072127138

T3 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

BT - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Y2 - 22 April 2019 through 25 April 2019

ER -

Tseng KY, You WX, Su P. Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8804704. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). doi: 10.1109/VLSI-TSA.2019.8804704

Evaluation of 2d negative-capacitance fets for low-voltage SRAM applications

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this