Estimating the Process Variation Effects of Stacked Gate All Around Si Nanosheet CFETs Using Artificial Neural Network Modeling Framework

Rajat Butola, Yiming Li*, Sekhar Reddy Kola, Min Hui Chuang, Chandni Akbar

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We for the first time report a novel machine learning (ML) approach to model the effects of varying process parameters on DC characteristics of stacked gate all around (GAA) Si nanosheet (NS) complementary-FETs (CFETs) using an artificial neural network (ANN) model. Process parameters that have predominant effects on device characteristics are considered and used as input features to the ANN model; and, their effects on DC characteristics are modeled. Major figures of merit (FoMs) are further extracted accurately from the transfer characteristics in much less computational time as compared to 3D device simulation. The performance of the ANN model is further evaluated using the coefficient of determination, R2-score, which is more than 96%. It shows that the ANN model successfully learned the information from the dataset; thus, the ANN model exhibits the competency in device modeling of emerging CFETs.

Original languageEnglish
Title of host publication2022 IEEE 22nd International Conference on Nanotechnology, NANO 2022
PublisherIEEE Computer Society
Pages170-173
Number of pages4
ISBN (Electronic)9781665452250
DOIs
StatePublished - 2022
Event22nd IEEE International Conference on Nanotechnology, NANO 2022 - Palma de Mallorca, Spain
Duration: 4 Jul 20228 Jul 2022

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2022-July
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference22nd IEEE International Conference on Nanotechnology, NANO 2022
Country/TerritorySpain
CityPalma de Mallorca
Period4/07/228/07/22

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