ESD robustness of 40-V CMOS devices with/without drift implant

Wei Jen Chang; Ming-Dou Ker; Tai Hsiang Lai; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/IRWS.2006.305237

ESD robustness of 40-V CMOS devices with/without drift implant

Wei Jen Chang^*, Ming-Dou Ker, Tai Hsiang Lai, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLPmeasured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.

Original language	English
Title of host publication	2006 IEEE International Integrated Reliability Workshop Final Report, IIRW
Pages	167-170
Number of pages	4
DOIs	https://doi.org/10.1109/IRWS.2006.305237
State	Published - 1 Dec 2006
Event	2006 IEEE International Integrated Reliability Workshop Final Report, IIRW - South Lake Tahoe, CA, United States Duration: 16 Oct 2006 → 19 Oct 2006

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report

Conference

Conference	2006 IEEE International Integrated Reliability Workshop Final Report, IIRW
Country/Territory	United States
City	South Lake Tahoe, CA
Period	16/10/06 → 19/10/06

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10.1109/IRWS.2006.305237

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@inproceedings{524a09ca359340eca193e0b25d94def0,

title = "ESD robustness of 40-V CMOS devices with/without drift implant",

abstract = "The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLPmeasured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.",

author = "Chang, {Wei Jen} and Ming-Dou Ker and Lai, {Tai Hsiang} and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/IRWS.2006.305237",

language = "English",

isbn = "1424402964",

series = "IEEE International Integrated Reliability Workshop Final Report",

pages = "167--170",

booktitle = "2006 IEEE International Integrated Reliability Workshop Final Report, IIRW",

note = "2006 IEEE International Integrated Reliability Workshop Final Report, IIRW ; Conference date: 16-10-2006 Through 19-10-2006",

}

Chang, WJ, Ker, M-D, Lai, TH, Tang, TH & Su, KC 2006, ESD robustness of 40-V CMOS devices with/without drift implant. in 2006 IEEE International Integrated Reliability Workshop Final Report, IIRW., 4098714, IEEE International Integrated Reliability Workshop Final Report, pp. 167-170, 2006 IEEE International Integrated Reliability Workshop Final Report, IIRW, South Lake Tahoe, CA, United States, 16/10/06. https://doi.org/10.1109/IRWS.2006.305237

ESD robustness of 40-V CMOS devices with/without drift implant. / Chang, Wei Jen; Ker, Ming-Dou; Lai, Tai Hsiang et al.
2006 IEEE International Integrated Reliability Workshop Final Report, IIRW. 2006. p. 167-170 4098714 (IEEE International Integrated Reliability Workshop Final Report).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Chang, Wei Jen

AU - Ker, Ming-Dou

AU - Lai, Tai Hsiang

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2006/12/1

Y1 - 2006/12/1

N2 - The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLPmeasured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.

AB - The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLPmeasured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.

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DO - 10.1109/IRWS.2006.305237

M3 - Conference contribution

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T3 - IEEE International Integrated Reliability Workshop Final Report

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BT - 2006 IEEE International Integrated Reliability Workshop Final Report, IIRW

T2 - 2006 IEEE International Integrated Reliability Workshop Final Report, IIRW

Y2 - 16 October 2006 through 19 October 2006

ER -

ESD robustness of 40-V CMOS devices with/without drift implant

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