ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ming-Dou Ker*, Chung-Yu Wu, Hun Hsien Chang, Chien Chang Huang, Chau Neng Wu, Ta Lee Yu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

Original languageEnglish
Pages98-101
Number of pages4
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong
Duration: 29 Jun 199629 Jun 1996

Conference

ConferenceProceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting
CityHong Kong, Hong Kong
Period29/06/9629/06/96

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