Abstract
Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.
Original language | English |
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Pages | 98-101 |
Number of pages | 4 |
DOIs | |
State | Published - 1 Dec 1996 |
Event | Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong Duration: 29 Jun 1996 → 29 Jun 1996 |
Conference
Conference | Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting |
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City | Hong Kong, Hong Kong |
Period | 29/06/96 → 29/06/96 |