Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.
|Number of pages||4|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong|
Duration: 29 Jun 1996 → 29 Jun 1996
|Conference||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting|
|City||Hong Kong, Hong Kong|
|Period||29/06/96 → 29/06/96|