ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Chien Chang Huang; Chau Neng Wu; Ta Lee Yu

doi:10.1109/HKEDM.1996.566328

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Chien Chang Huang, Chau Neng Wu, Ta Lee Yu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

Original language	English
Pages	98-101
Number of pages	4
DOIs	https://doi.org/10.1109/HKEDM.1996.566328
State	Published - 1 Dec 1996
Event	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong Duration: 29 Jun 1996 → 29 Jun 1996

Conference

Conference	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting
City	Hong Kong, Hong Kong
Period	29/06/96 → 29/06/96

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10.1109/HKEDM.1996.566328

Cite this

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abstract = "Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Huang, {Chien Chang} and Wu, {Chau Neng} and Yu, {Ta Lee}",

year = "1996",

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doi = "10.1109/HKEDM.1996.566328",

language = "English",

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AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Huang, Chien Chang

AU - Wu, Chau Neng

AU - Yu, Ta Lee

PY - 1996/12/1

Y1 - 1996/12/1

N2 - Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

AB - Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

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U2 - 10.1109/HKEDM.1996.566328

DO - 10.1109/HKEDM.1996.566328

M3 - Paper

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T2 - Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting

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ER -

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Abstract

Conference

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