ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

T. Y. Chen; Ming-Dou Ker

doi:10.1109/VTSA.2001.934527

ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

T. Y. Chen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the sub-quarter-micron CMOS process.

Original language	English
Pages	232-235
Number of pages	4
DOIs	https://doi.org/10.1109/VTSA.2001.934527
State	Published - 18 Apr 2001
Event	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan Duration: 18 Apr 2001 → 20 Apr 2001

Conference

Conference	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Country/Territory	Taiwan
City	Hsinchu
Period	18/04/01 → 20/04/01

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title = "ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design",

abstract = "The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the sub-quarter-micron CMOS process.",

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AB - The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the sub-quarter-micron CMOS process.

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ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

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