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ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology
Ming-Dou Ker
, Chau Neng Wu
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Corresponding author for this work
Institute of Electronics
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Dive into the research topics of 'ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology'. Together they form a unique fingerprint.
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Keyphrases
Slew Rate
100%
ESD Protection
100%
Output Buffer
100%
Field Oxide Device
100%
CMOS SRAM
100%
Coupled Field
62%
ESD Protection Design
37%
Device Structure
25%
P-well
25%
Wafer
12%
Transistor
12%
Trigger Voltage
12%
Layout Area
12%
Breakdown Voltage
12%
Circuit Performance
12%
Protection Efficiency
12%
Deep Submicron Technology
12%
Series Resistor
12%
Transient Voltage
12%
Salicide
12%
Snapback
12%
Wire Bonding
12%
Coupling Capacitor
12%
NMOS Transistor
12%
Parasitic Capacitor
12%
Double Diode Structures
12%
Engineering
Slew Rate
100%
Controlled Output
100%
Device Structure
66%
Transients
33%
Breakdown Voltage
33%
Coupling Capacitor
33%
Circuit Performance
33%
Bonding Wire
33%
Series Resistor
33%
Material Science
Oxide Compound
100%
Transistor
25%
Capacitor
25%
Electronic Circuit
12%