ESD protection for output pad with well-coupled field-oxide device in 0.5-/nm CMOS technology

Chau Neng Wu; Ming-Dou Ker

doi:10.1109/16.556162

ESD protection for output pad with well-coupled field-oxide device in 0.5-/nm CMOS technology

Chau Neng Wu^*, Ming-Dou Ker

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A well-coupled field-oxide device (WCFOD) is first proposed to effectively improve Electrostatic Discharge (ESD) robustness of the output pad in a 0.5-μm CMOS process. ESD-transient voltage is coupled to the bulk of field-oxide device through a parasitic capacitor to trigger on the lateral bipolar action of the field-oxide device. This WCFOD has been practically implemented in a 256-K high-speed SRAM product to sustain HBM ESD stress up to 6500 V.

Original language	English
Pages (from-to)	503-505
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	44
Issue number	3
DOIs	https://doi.org/10.1109/16.556162
State	Published - 1997

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title = "ESD protection for output pad with well-coupled field-oxide device in 0.5-/nm CMOS technology",

abstract = "A well-coupled field-oxide device (WCFOD) is first proposed to effectively improve Electrostatic Discharge (ESD) robustness of the output pad in a 0.5-μm CMOS process. ESD-transient voltage is coupled to the bulk of field-oxide device through a parasitic capacitor to trigger on the lateral bipolar action of the field-oxide device. This WCFOD has been practically implemented in a 256-K high-speed SRAM product to sustain HBM ESD stress up to 6500 V.",

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AU - Ker, Ming-Dou

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AB - A well-coupled field-oxide device (WCFOD) is first proposed to effectively improve Electrostatic Discharge (ESD) robustness of the output pad in a 0.5-μm CMOS process. ESD-transient voltage is coupled to the bulk of field-oxide device through a parasitic capacitor to trigger on the lateral bipolar action of the field-oxide device. This WCFOD has been practically implemented in a 256-K high-speed SRAM product to sustain HBM ESD stress up to 6500 V.

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ESD protection for output pad with well-coupled field-oxide device in 0.5-/nm CMOS technology

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