ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

Ming-Dou Ker; Wei Jen Chang; Chang Tzu Wang; Wen Yi Chen

doi:10.1109/ISSCC.2006.1696284

ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

Ming-Dou Ker^*, Wei Jen Chang, Chang Tzu Wang, Wen Yi Chen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.

Original language	English
Title of host publication	2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs	https://doi.org/10.1109/ISSCC.2006.1696284
State	Published - 1 Dec 2006
Event	2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 6 Feb 2006 → 9 Feb 2006

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	6/02/06 → 9/02/06

Access to Document

10.1109/ISSCC.2006.1696284

Cite this

@inproceedings{6607788fc13246458f1808a571fac7b0,

title = "ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS",

abstract = "An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.",

author = "Ming-Dou Ker and Chang, {Wei Jen} and Wang, {Chang Tzu} and Chen, {Wen Yi}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ISSCC.2006.1696284",

language = "English",

isbn = "1424400791",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

booktitle = "2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",

note = "2006 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2006 Through 09-02-2006",

}

Ker, M-D, Chang, WJ, Wang, CT & Chen, WY 2006, ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS. in 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 1696284, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 6/02/06. https://doi.org/10.1109/ISSCC.2006.1696284

ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS. / Ker, Ming-Dou; Chang, Wei Jen; Wang, Chang Tzu et al.
2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2006. 1696284 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

AU - Ker, Ming-Dou

AU - Chang, Wei Jen

AU - Wang, Chang Tzu

AU - Chen, Wen Yi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.

AB - An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.

UR - http://www.scopus.com/inward/record.url?scp=34250620367&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2006.1696284

DO - 10.1109/ISSCC.2006.1696284

M3 - Conference contribution

AN - SCOPUS:34250620367

SN - 1424400791

SN - 9781424400799

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers

T2 - 2006 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2006 through 9 February 2006

ER -

ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this