ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations

Abstract

A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12 V (VSS-12 V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.

Original languageEnglish
Pages (from-to)283-286
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: 7 Sep 199710 Sep 1997

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