ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

Chia Tsen Dai, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE International System on Chip Conference, SOCC 2015
EditorsThomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages380-383
Number of pages4
ISBN (Electronic)9781467390934
DOIs
StatePublished - 12 Feb 2016
Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
Duration: 8 Sep 201511 Sep 2015

Publication series

NameInternational System on Chip Conference
Volume2016-February
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference28th IEEE International System on Chip Conference, SOCC 2015
Country/TerritoryChina
CityBeijing
Period8/09/1511/09/15

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