ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers

Ming-Dou Ker*, Wei Jen Chang

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    30 Scopus citations

    Abstract

    Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-VSS, negative-to-VSS, positive-to-VDD, and negative-to-VDD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-m CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.

    Original languageEnglish
    Pages (from-to)1409-1416
    Number of pages8
    JournalIEEE Transactions on Electron Devices
    Volume55
    Issue number6
    DOIs
    StatePublished - Jun 2008

    Keywords

    • Electrostatic discharge (ESD)
    • High-voltagetolerant ESD clamp circuit
    • I/O
    • Mixed-voltage secondary
    • On-chip ESD bus
    • Secondary breakdown current (I) substrate-triggered technique

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