ESD protection design with lateral DMOS transistor in 40-V BCD technology

Chang Tzu Wang; Ming-Dou Ker; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/IPFA.2010.5532308

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Chang Tzu Wang^*, Ming-Dou Ker, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

Original language	English
Title of host publication	IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs	https://doi.org/10.1109/IPFA.2010.5532308
State	Published - 15 Sep 2010
Event	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 5 Jul 2010 → 9 Jul 2010

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
Country/Territory	Singapore
City	Singapore
Period	5/07/10 → 9/07/10

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10.1109/IPFA.2010.5532308

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Wang, C. T., Ker, M-D., Tang, T. H., & Su, K. C. (2010). ESD protection design with lateral DMOS transistor in 40-V BCD technology. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits [5532308] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2010.5532308

@inproceedings{04c14ef4d02b4232a9e448c0530c1946,

title = "ESD protection design with lateral DMOS transistor in 40-V BCD technology",

abstract = "ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.",

author = "Wang, {Chang Tzu} and Ming-Dou Ker and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2010",

month = sep,

day = "15",

doi = "10.1109/IPFA.2010.5532308",

language = "English",

isbn = "9781424455973",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits",

note = "17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 ; Conference date: 05-07-2010 Through 09-07-2010",

}

Wang, CT, Ker, M-D, Tang, TH & Su, KC 2010, ESD protection design with lateral DMOS transistor in 40-V BCD technology. in IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits., 5532308, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010, Singapore, Singapore, 5/07/10. https://doi.org/10.1109/IPFA.2010.5532308

ESD protection design with lateral DMOS transistor in 40-V BCD technology. / Wang, Chang Tzu; Ker, Ming-Dou; Tang, Tien Hao et al.
IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532308 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection design with lateral DMOS transistor in 40-V BCD technology

AU - Wang, Chang Tzu

AU - Ker, Ming-Dou

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2010/9/15

Y1 - 2010/9/15

N2 - ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

AB - ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

UR - http://www.scopus.com/inward/record.url?scp=77956421822&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2010.5532308

DO - 10.1109/IPFA.2010.5532308

M3 - Conference contribution

AN - SCOPUS:77956421822

SN - 9781424455973

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

BT - IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits

T2 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010

Y2 - 5 July 2010 through 9 July 2010

ER -

Wang CT, Ker M-D, Tang TH, Su KC. ESD protection design with lateral DMOS transistor in 40-V BCD technology. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532308. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2010.5532308

ESD protection design with lateral DMOS transistor in 40-V BCD technology

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