Abstract
An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.
Original language | English |
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Article number | 5604306 |
Pages (from-to) | 3395-3404 |
Number of pages | 10 |
Journal | IEEE Transactions on Electron Devices |
Volume | 57 |
Issue number | 12 |
DOIs | |
State | Published - 1 Dec 2010 |
Keywords
- Bipolar CMOS DMOS (BCD) process
- ESD protection
- electrostatic discharge (ESD)
- latchup