ESD protection design with latchup-free immunity in 120V SOI process

Yi Jie Huang; Ming-Dou Ker; Yeh Jen Huang; Chun Chien Tsai; Yeh Ning Jou; Geeng Lih Lin

doi:10.1109/S3S.2015.7333481

ESD protection design with latchup-free immunity in 120V SOI process

Yi Jie Huang, Ming-Dou Ker, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.

Original language	English
Title of host publication	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509002597
DOIs	https://doi.org/10.1109/S3S.2015.7333481
State	Published - 20 Nov 2015
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: 5 Oct 2015 → 8 Oct 2015

Publication series

Name	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conference

Conference	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/Territory	United States
City	Rohnert Park
Period	5/10/15 → 8/10/15

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10.1109/S3S.2015.7333481

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Huang, Y. J., Ker, M-D., Huang, Y. J., Tsai, C. C., Jou, Y. N., & Lin, G. L. (2015). ESD protection design with latchup-free immunity in 120V SOI process. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 [7333481] (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2015.7333481

@inproceedings{5d6f11df51644aa7b42dccb753d37534,

title = "ESD protection design with latchup-free immunity in 120V SOI process",

abstract = "Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.",

author = "Huang, {Yi Jie} and Ming-Dou Ker and Huang, {Yeh Jen} and Tsai, {Chun Chien} and Jou, {Yeh Ning} and Lin, {Geeng Lih}",

year = "2015",

month = nov,

day = "20",

doi = "10.1109/S3S.2015.7333481",

language = "English",

series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

address = "United States",

note = "null ; Conference date: 05-10-2015 Through 08-10-2015",

}

Huang, YJ, Ker, M-D, Huang, YJ, Tsai, CC, Jou, YN & Lin, GL 2015, ESD protection design with latchup-free immunity in 120V SOI process. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333481, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 5/10/15. https://doi.org/10.1109/S3S.2015.7333481

ESD protection design with latchup-free immunity in 120V SOI process. / Huang, Yi Jie; Ker, Ming-Dou; Huang, Yeh Jen et al.

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333481 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection design with latchup-free immunity in 120V SOI process

AU - Huang, Yi Jie

AU - Ker, Ming-Dou

AU - Huang, Yeh Jen

AU - Tsai, Chun Chien

AU - Jou, Yeh Ning

AU - Lin, Geeng Lih

PY - 2015/11/20

Y1 - 2015/11/20

N2 - Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.

AB - Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.

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U2 - 10.1109/S3S.2015.7333481

DO - 10.1109/S3S.2015.7333481

M3 - Conference contribution

AN - SCOPUS:84961768939

T3 - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

BT - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 5 October 2015 through 8 October 2015

ER -

Huang YJ, Ker M-D, Huang YJ, Tsai CC, Jou YN, Lin GL. ESD protection design with latchup-free immunity in 120V SOI process. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333481. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/S3S.2015.7333481

ESD protection design with latchup-free immunity in 120V SOI process

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