ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Ming-Dou Ker; Chyh Yih Chang; Yi Shu Chang

doi:10.1109/ASIC.2002.1158062

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Ming-Dou Ker, Chyh Yih Chang, Yi Shu Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.

Original language	English
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	234-238
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158062
State	Published - 1 Jan 2002
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: 25 Sep 2002 → 28 Sep 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Conference

Conference	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	25/09/02 → 28/09/02

Access to Document

10.1109/ASIC.2002.1158062

Cite this

Ker, M.-D., Chang, C. Y., & Chang, Y. S. (2002). ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 234-238). Article 1158062 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158062

Ker, Ming-Dou ; Chang, Chyh Yih ; Chang, Yi Shu. / ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 234-238 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

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abstract = "This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.",

author = "Ming-Dou Ker and Chang, {Chyh Yih} and Chang, {Yi Shu}",

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Ker, M-D, Chang, CY & Chang, YS 2002, ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158062, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 234-238, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 25/09/02. https://doi.org/10.1109/ASIC.2002.1158062

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. / Ker, Ming-Dou; Chang, Chyh Yih; Chang, Yi Shu.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 234-238 1158062 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.

AB - This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.

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Ker MD, Chang CY, Chang YS. ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 234-238. 1158062. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158062

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

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