TY - GEN
T1 - ESD protection design on T/R switch with embedded SCR in CMOS process
AU - Hung, Tao Yi
AU - Ker, Ming-Dou
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/5
Y1 - 2017/10/5
N2 - ESD protection design for the RF transmit/receive switch (T/R switch) with embedded silicon-controlled rectifier (SCR) is proposed, where the SCR device is embedded in the ESD diode and the transistors of T/R switch by layout skill. Silicon chip verified in a 90-nm CMOS process has been measured by TLP and HBM ESD test to confirm its efficiency for ESD protection. The parasitic capacitance from the ESD devices was also measured. Failure analysis by SEM was performed to find the burned-out site on the T/R switch with the proposed design. From the failure analysis SEM pictures, the embedded SCR in the proposed design is actually triggered on to discharge ESD current.
AB - ESD protection design for the RF transmit/receive switch (T/R switch) with embedded silicon-controlled rectifier (SCR) is proposed, where the SCR device is embedded in the ESD diode and the transistors of T/R switch by layout skill. Silicon chip verified in a 90-nm CMOS process has been measured by TLP and HBM ESD test to confirm its efficiency for ESD protection. The parasitic capacitance from the ESD devices was also measured. Failure analysis by SEM was performed to find the burned-out site on the T/R switch with the proposed design. From the failure analysis SEM pictures, the embedded SCR in the proposed design is actually triggered on to discharge ESD current.
UR - http://www.scopus.com/inward/record.url?scp=85045046043&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2017.8060079
DO - 10.1109/IPFA.2017.8060079
M3 - Conference contribution
AN - SCOPUS:85045046043
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 1
EP - 6
BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Y2 - 4 July 2017 through 7 July 2017
ER -