ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu; Hun Hsien Chang

doi:10.1109/ASIC.1999.806533

ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Ming-Dou Ker, Tung Yang Chen, Chung-Yu Wu, Hun Hsien Chang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.

Original language	English
Title of host publication	Proceedings - 12th Annual IEEE International ASIC/SOC Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	352-356
Number of pages	5
ISBN (Electronic)	0780356322, 9780780356320
DOIs	https://doi.org/10.1109/ASIC.1999.806533
State	Published - 1 Jan 1999
Event	12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: 15 Sep 1999 → 18 Sep 1999

Publication series

Name	Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Conference

Conference	12th Annual IEEE International ASIC/SOC Conference
Country/Territory	United States
City	Washington
Period	15/09/99 → 18/09/99

Access to Document

10.1109/ASIC.1999.806533

Cite this

Ker, M.-D., Chen, T. Y., Wu, C.-Y., & Chang, H. H. (1999). ESD protection design on analog pin with very low input capacitance for RF or current-mode applications. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 352-356). Article 806533 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806533

@inproceedings{aa641f465fcd4ebbb49268310c19eeb8,

title = "ESD protection design on analog pin with very low input capacitance for RF or current-mode applications",

abstract = "An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu and Chang, {Hun Hsien}",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/ASIC.1999.806533",

language = "English",

series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "352--356",

booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

address = "美國",

note = "12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",

}

Ker, M-D, Chen, TY, Wu, C-Y & Chang, HH 1999, ESD protection design on analog pin with very low input capacitance for RF or current-mode applications. in Proceedings - 12th Annual IEEE International ASIC/SOC Conference., 806533, Proceedings - 12th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers Inc., pp. 352-356, 12th Annual IEEE International ASIC/SOC Conference, Washington, United States, 15/09/99. https://doi.org/10.1109/ASIC.1999.806533

ESD protection design on analog pin with very low input capacitance for RF or current-mode applications. / Ker, Ming-Dou; Chen, Tung Yang; Wu, Chung-Yu et al.
Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 352-356 806533 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

AU - Ker, Ming-Dou

AU - Chen, Tung Yang

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

PY - 1999/1/1

Y1 - 1999/1/1

N2 - An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.

AB - An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.

UR - http://www.scopus.com/inward/record.url?scp=77950849960&partnerID=8YFLogxK

U2 - 10.1109/ASIC.1999.806533

DO - 10.1109/ASIC.1999.806533

M3 - Conference contribution

AN - SCOPUS:77950849960

T3 - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

SP - 352

EP - 356

BT - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th Annual IEEE International ASIC/SOC Conference

Y2 - 15 September 1999 through 18 September 1999

ER -

Ker MD, Chen TY, Wu CY, Chang HH. ESD protection design on analog pin with very low input capacitance for RF or current-mode applications. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc. 1999. p. 352-356. 806533. (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). doi: 10.1109/ASIC.1999.806533

ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this