ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications

Tao Yi Hung; Ming-Dou Ker

doi:10.1109/ISCAS.2019.8702743

ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications

Tao Yi Hung, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-µm CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the positive-to-V_SS stress and 5 kV under the negative-to-V_SS stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.

Original language	English
Title of host publication	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	5
ISBN (Electronic)	9781728103976
DOIs	https://doi.org/10.1109/ISCAS.2019.8702743
State	Published - 26 May 2019
Event	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: 26 May 2019 → 29 May 2019

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2019-May
ISSN (Print)	0271-4310

Conference

Conference	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/Territory	Japan
City	Sapporo
Period	26/05/19 → 29/05/19

Keywords

ESD protection design
High-linearity switch
Power-rail ESD clamp circuit
SPDT
T/R switch
Transient detection circuit

Access to Document

10.1109/ISCAS.2019.8702743

Cite this

Hung, T. Y., & Ker, M.-D. (2019). ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings Article 8702743 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702743

@inproceedings{b0fc7c49e4704723ab159c914254af50,

title = "ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications",

abstract = "Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-µm CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the positive-to-VSS stress and 5 kV under the negative-to-VSS stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.",

keywords = "ESD protection design, High-linearity switch, Power-rail ESD clamp circuit, SPDT, T/R switch, Transient detection circuit",

author = "Hung, {Tao Yi} and Ming-Dou Ker",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE; 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 ; Conference date: 26-05-2019 Through 29-05-2019",

year = "2019",

month = may,

day = "26",

doi = "10.1109/ISCAS.2019.8702743",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings",

address = "美國",

}

Hung, TY & Ker, M-D 2019, ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702743, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 26/05/19. https://doi.org/10.1109/ISCAS.2019.8702743

ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications. / Hung, Tao Yi; Ker, Ming-Dou.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702743 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications

AU - Hung, Tao Yi

AU - Ker, Ming-Dou

PY - 2019/5/26

Y1 - 2019/5/26

N2 - Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-µm CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the positive-to-VSS stress and 5 kV under the negative-to-VSS stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.

AB - Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-µm CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the positive-to-VSS stress and 5 kV under the negative-to-VSS stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.

KW - ESD protection design

KW - High-linearity switch

KW - Power-rail ESD clamp circuit

KW - SPDT

KW - T/R switch

KW - Transient detection circuit

UR - http://www.scopus.com/inward/record.url?scp=85066792305&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2019.8702743

DO - 10.1109/ISCAS.2019.8702743

M3 - Conference contribution

AN - SCOPUS:85066792305

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019

Y2 - 26 May 2019 through 29 May 2019

ER -

ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this