ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Win

doi:10.1109/ISCAS.2001.922347

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker, Tung Yang Chen, Chung-Yu Win

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

20 Scopus citations

Abstract

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	754-757
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922347
State	Published - 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 6 May 2001 → 9 May 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	6/05/01 → 9/05/01

Access to Document

10.1109/ISCAS.2001.922347

Cite this

Ker, M.-D., Chen, T. Y., & Win, C.-Y. (2001). ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 754-757). Article 922347 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922347

@inproceedings{3365b775eb4c471988632bb0db5ca21c,

title = "ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique",

abstract = "A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Win",

year = "2001",

doi = "10.1109/ISCAS.2001.922347",

language = "English",

isbn = "0780366859",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "754--757",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

Ker, M-D, Chen, TY & Win, C-Y 2001, ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922347, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 754-757, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.922347

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique. / Ker, Ming-Dou; Chen, Tung Yang; Win, Chung-Yu.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 754-757 922347 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.

AB - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.

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DO - 10.1109/ISCAS.2001.922347

M3 - Conference contribution

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SN - 0780366859

SN - 9780780366855

T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

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Ker MD, Chen TY, Win CY. ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 754-757. 922347. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings). doi: 10.1109/ISCAS.2001.922347

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

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