Abstract
A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.
Original language | English |
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Article number | 922347 |
Pages (from-to) | IV754-IV757 |
Number of pages | 4 |
Journal | Materials Research Society Symposium - Proceedings |
Volume | 626 |
State | Published - Apr 2000 |
Event | Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 Apr 2000 → 27 Apr 2000 |